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| SIP11203DB Vishay Siliconix SiP11203 Demonstration Board DEMONSTRATION BOARD TEST SETUP This demonstration board test setup information details the test procedure for using the SiP11203 demonstration board and its associated host board. The demonstration board is plugged vertically into the host board. Only one orientation is possible for correct plugin. The input and output power leads and an optional enable lead are wired into the host board connectors as shown in Figure 1. A mechanical toggle switch is also available on the host board for manual enabling and disabling of the demonstration board. The host board is configured by default for manual switch toggling of enable/disable. If an electrical control signal is preferred, this can be wired into the enable connector J2. However, in this case the zero ohm link connected in the R4 position must be removed and reconnected in the R1 position, which is vacant by default. A 5 V input to the enable pin disables the demonstration board and a 0 V or open circuit input signal causes the demonstration board to be enabled. Test pins are available on the host board, at the input, output, and enable pins, for the easy connection of scope probes. These wiring connections are depicted in Figure 1. The input connections should be wired as closely as possible to the power supply, using cable rated at 2 A or more. However, lead lengths of up to a meter or two are probably acceptable. If the leads are significantly longer, a second input decoupling capacitor should be connected in position C1, which is left blank by default. At the load side, four 8 A rated wires should be connected from both +Vout and -Vout terminals to the load. The Vsense terminals can be connected remotely to the load terminals for good regulation at the load, but this is not essential, as the Vsense terminals are connected to the output terminals through 4.7 resistors on the demonstration board. A small fan should be placed adjacent to the host board, blowing cooling air over both vertical faces of the demonstration board. There is over temperature protection within the demonstration board, so the system will function without fan cooling, but the demonstration board will disable operation if the PCB temperature exceeds 85 C, and will re-enable once the temperature drops to 75 C. The rated input voltage range is 36 V - 75 V, and the converter can operate at input voltage levels up to 100 V for 100 ms. The maximum rated load is 50 W. The output voltage is regulated to 3.3 V with an output load current range of 0 A - 15 A. FEATURES * High efficiency, > 87 % at full rated load current * Delivers up to 15 amps of output current with minimal de-rating - no heat sink required * Wide input voltage range: 35 V - 75 V, with 100 V 100 ms input voltage transient capability * No minimum load requirement means no preload resistors required * Remote sense for the output voltage compensates for output distribution drops * On/Off control referenced to input side * Input under-voltage lockout disables converter at low input voltage conditions * Output short circuit protection protects converter and load from permanent damage and consequent hazardous conditions * Output over-voltage protection protects load from damaging voltages * Thermal shutdown protects converter from abnormal environmental conditions To load Airflow Direction Enable (optional) VinVin+ Figure 1. SiP11203 Test Board Layout The information shown here is a preliminary product proposal, not a commercial product data sheet. Vishay Siliconix is not committed to produce this or any similar product. This information should not be used for design purposes, nor construed as an offer to furnish or sell such products Document Number: 74254 S-60997-Rev. A, 12-Jun-06 www.vishay.com 1 SIP11203DB Vishay Siliconix DEMONSTRATION BOARD INFORMATION The demonstration board is an 8-layer board in the eighth-brick form factor, manufactured in 2 oz copper. The circuit schematics for the SiP11203 demonstration board are illustrated in Figure 2 and Figure 3. Power Conversion Circuit The primary power circuit is a half-bridge configuration with a 4:1 turns ratio transformer, T2, connected between the switching pole of the half-bridge and the center tap of the capacitive input filter. The half-bridge capacitors C10 to C17 are configured as two series-connected banks of four parallel-connected 1 F ceramic capacitors. Resistors R20 and R21 provide voltage balancing and discharge paths for the capacitor banks. The primary side half-bridge circuit is driven using the Si9122 controller IC. This generates both the primary MOSFET drive signals as well as the timing signals for the secondary side synchronous MOSFETs. These timing signals, SRL and SRH, are coupled to the secondary through the pulse transformer T1. The SiP11203 uses the timing information to drive the secondary synchronous MOSFETs Q3 to Q6. The secondary side synchronous MOSFETs rectify the center-tapped transformer secondary voltage, the output of which is filtered by the LC-filter L1C28-C31. L1 is a 900 nH inductor, C28 is a 22 F tantalum capacitor and C31 is a 100 F ceramic capacitor. RCD snubbers are placed across the synchronous rectifier MOSFETs in order to clamp the secondary leakage inductance voltage spike and reduce switching losses. Some of the main switching circuit waveforms are plotted in Figure 4. The converter efficiency over the line and load range is depicted in Figure 5. Note that these efficiency readings do not take account of the voltage drops across the plug-in pins of the demonstration board. Bias Supply The primary bias supply, VCC, is a 10.4 V supply that is generated from an auxiliary winding, L1-B of the output filter inductor. The auxiliary winding turns ratio is 3.333:1, resulting in an auxiliary winding voltage of approximately 11 V during the inductor current rampdown period. This voltage is rectified and filtered by diode D4 and capacitors C23 and C26. During startup and other conditions such as short-circuited output, the primary bias voltage is supplied by means of a 9.1 V linear pre-regulator on the Si9122 controller. An external PNP pre-regulator transistor Q8 is provided to divert the main power dissipation away from the Si9122 during the period when the 9.1 V bias is being utilised. The rise of VCC and VO during startup is depicted in Figure 6 (a). It is clear that converter operation commences when VCC reaches 9.1 V and, the change to the auxiliary bias level can also be seen. Figure 2. SiP11203 Demonstration Board Primary Side Schematic www.vishay.com 2 Document Number: 74254 S-60997-Rev. A, 12-Jun-06 SIP11203DB Vishay Siliconix Figure 3. SiP11203 Demonstration Board Secondary Side Schematic Primary Gate drive Waveform (10 V/DIV) Input of Pulse Transformer (10 V/DIV) Primary Switching Waveform (20 V/DIV) Output of Pulse Transformer (5 V/DIV) Output of SiP11203 Driver (5 V/DIV) Output of SiP11203 Driver (5 V/DIV) Drain of Secondary MOSFET (10 V/DIV) 1.00 S/DIV (a) Drain of Secondary MOSFET (10 V/DIV) 1.00 S/DIV (b) Figure 4. (a) Primary switching waveforms and the secondary switching waveforms. (b) The gate driving waveform and the secondary switching waveform. Document Number: 74254 S-60997-Rev. A, 12-Jun-06 www.vishay.com 3 SIP11203DB Vishay Siliconix 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 2A 4A 35 Vin 48 Vin Eff (%) 75 Vin 6A 8 A 10 A Io (A) 12 A 14 A 15 A Figure 5. Converter efficiency over line voltage and load range The secondary bias supply (VIN on the SiP11203) is provided from VCC via the timing signals SRH and SRL generated by the Si9122. These timing signals drive the positive and negative terminals of the primary winding of pulse transformer T1. This transformer has a step-down ratio of 4:3 for each secondary winding. The secondary windings are center tapped, with a capacitive filter placed at the center tap point, and rectifier diodes anode-connected to ground, connected to each end of the secondary windings. This arrangement means that the timing information is coupled to the SiP11203, while a bias voltage is also available at the center-tap to power the SiP11203. This bias voltage VIN is used to power the output drivers OUTA and OUTB. It is also internally regulated to a 5 V bias, VL, which powers the other internal circuitry on the SiP11203. The voltage on one of the pulse transformer secondary windings wrt ground is shown in Figure 6 (b). It can be seen from this that the center-tap voltage, which provides the VIN supply to the SiP11203, is equal to the average value of the secondary voltage. Output of pulse tansformer (2 V/DIV) Primary VCC Start Up Waveform (2 V/DIV) VIN for SiP11203 (2 V/DIV) Output Voltage Start Up Waveform (1 V/DIV) 1.00 mS/DIV (a) 1.00 S/DIV (b) Figure 6. (a)VCC, VO, during startup (b)Pulse Transformer Secondary Voltage, Pulse Transformer Center-Tap Voltage, VIN. Magnetic Component The main power transformer structure is illustrated in Figure 7. The multilayer PCB layout is described in Table 1. The primary magnetizing inductance is between 11 H and 15 H, and the turns ratio is 4:1:1. The core is a combination of an E14/3.5/5 core and its associated I-plate in 3F3 material. The output filter inductor structure is illustrated in Figure 8 and the multilayer PCB layout is described in Table 2. The inductor has 2 sections of 3 turns connected in parallel, with a custom ground center gap to yield an inductance value between 850 nH and 900 nH. The auxiliary winding is constructed of 10 turns, divided between 2 layers, resulting in a 10:3 turns ratio between the auxiliary and main windings. The core is a combination of an E14/ 3.5/5 core and its associated I-plate in 3F3 material. www.vishay.com 4 P1 P2 Primary P3 S1 S2 Secondary S3 S4 Secondary P4 Figure 7. Power Transformer Structure Document Number: 74254 S-60997-Rev. A, 12-Jun-06 SIP11203DB Vishay Siliconix MULTILAYER PCB DESIGN FOR POWER TRANSFORMER Layer 1 2 3 4 5 6 7 8 Winding P1 S1 P2 S2 P3 S3 P4 S4 Table 1. Pc No. of Turns 1 1 1 1 1 1 1 1 Sa Pa Sb Pb Sc B1 B2 Vbias Sd L1 L4 L2 L5 L3 VO L6 Figure 9. Pulse Transformer Structure Figure 8. Power Inductor Structure MULTILAYER PCB DESIGN FOR POWER INDUCTOR Layer 1 2 3 4 5 6 7 8 Winding L1 L2 L3 B1 B2 L4 L5 L6 Table 2. No. of Turns 1 1 1 5 5 1 1 1 Controller The SiP11203 possesses a voltage reference and Op Amp, which can be used to control the output voltage. The reference voltage VREF is compared with the scaled output voltage, and the compensated error voltage drives the opto-coupler diode U3-A. The current in the opto-coupler transistor U3-B is converted to a voltage signal by R13 and this signal is applied to the EP pin of the Si9122, where it is converted to a PWM output. The compensation structure is depicted in Figure 10. Vo R8 C25 C29 R5 + - The pulse transformer structure is illustrated in Figure 9. The multilayer PCB layout is described in Table 3. The primary magnetizing inductance is between 90 H and 130 H, and the turn ratio is 8:6:6. The core is a combination of two E8.8 cores in high permeability T38 material from EPCOS. These cores must be aligned very carefully, and glued together while clamped, with no glue being placed between the core legs, in order to ensure the required magnetizing inductance. If the magnetizing inductance is too low, the Si9122 will be overloaded, and the circuit will not function. MULTILAYER PCB DESIGN FOR PULSE TRANSFORMER Layer 1 2 3 4 5 6 7 8 Winding Pa Sa Sb Pb Sc Sd Pc Table 3. No. of Turns 3 3 2 3 3 3 3 - R1 R6 R2//R37 SiP11203 Vref R7 C2 EP U3 R13 C7 C1 Vcc R9 C4 Figure 10. Controller Compensation Structure The equation describing the compensation circuitry is: R 13 CTR R9 (1 + S R 7C 1)(1 + S R9C4) S R 6 (C 1 + C 2 )(1 + S R 13 C 7 ) (1 + S R 2 C1C2 C1 + C2 ) Document Number: 74254 S-60997-Rev. A, 12-Jun-06 www.vishay.com 5 SIP11203DB Vishay Siliconix Where CTR is the current transfer ratio of the optocoupler, and where R5 = R6, R8 = R7, C25 = C1 and C29 = C2. An origin pole, two zeroes and two poles can be potentially synthesized. Hence, either Type 2 or Type 3 compensation can be implemented. In the demonstration board, Type 2 compensation is implemented, resulting in a bandwidth in the region of 10 kHz. The transient response of the output voltage to 5 A load steps is depicted in Figure 11. Startup and Shutdown The startup sequence is described as follows: 1. The primary side duty cycle ramps up from its minimum value at rate determined by the charging of the soft-start capacitor C20. At this point, the converter is operating open loop. 2. Simultaneously, the bias voltage VIN for the SiP11203 increases as decoupling capacitor C8 is charged from SRH and SRL through the pulse transformer. Regulated voltage VL also increases as C8 is charged. 3. Once the voltage on the VL pin of the SiP11203 has reached 3.5 V, the internal circuitry on the IC (apart from output drivers) becomes functional, and the converter begins to regulate. However, the reference voltage is still at zero. 4. When VL reaches 4.5 V, the reference voltage ramps towards 1.225 V, at rate determined by the charging of C5. The output voltage should then track the reference voltage increase. The various time constants described above must be designed and synchronized to ensure a smooth startup sequence for the converter. The SiP11203 also incorporates a functionality whereby the on-time of the synchronous MOSFETs is increased gradually at startup, in order to minimize oscillation and steps in the output voltage. This is the phase-in function of SiP11203. This is accomplished by variation of R10. This functionality is disabled if the RDEL pin of the SiP11203 is tied to VL, by connecting a zero ohm link in the R33 position. In Figure 12(a), the two distinct stages of startup can be seen, where the output initially rises open loop, and subsequently follows the reference voltage. The SiP11203 incorporates a controlled shutdown feature, whereby the gates of the synchronous MOSFETs are pulled to ground gradually once it is ascertained that a shutdown event has indeed occurred. This prevents destructive under-voltage transients due to LCfilter oscillation that normally occurs on shutdown when both gate voltages remain high. Variation of the shutdown detection time and gate discharge time is accomplished by variation of R12 and C6. The controlled shutdown and minimal under-voltage swing are depicted in Figure 12(b). The maximum under-voltage seen is 0.7 V. Output Voltage (200 mV/DIV) Output Voltage (200 mV/DIV) 50.0 S/DIV (a) 50.0 S/DIV (b) Figure 11. (a) Output voltage response to 5 A step load increase (b) Output voltage response to 5 A step load decrease (both ac coupling; 200 mV/div- 12.5 A 7.5 A, 48 V input, 200 mA/S slew rate) www.vishay.com 6 Document Number: 74254 S-60997-Rev. A, 12-Jun-06 SIP11203DB Vishay Siliconix Secondary Reference Voltage VREF(0.5 V/DIV) VCPD Waveform (1 V/DIV) Output Voltage Start Up Waveform (1 V/DIV) Output Voltage (1 V/DIV) Secondary Synchronous MOSFET Gate Waveform (2 V/DIV) 2.00 S/DIV (b) 500 S/DIV (a) Figure 12. (a) Rise of VREF and VO during startup (b) VCpd, OUTA and VO during shutdown (both at 48 V input and 15 A load) Protection Over-current detection and protection is performed within the Si9122 in conjunction with the current sense resistor R22. Over-voltage protection is incorporated in the SiP11203 and can be set using the potential divider R3-R4. Startup into an over-voltage is illustrated in Figure 13, where the over-voltage is discharged, and the switching and reference voltage are then disabled. Thermal protection is implemented in IC U4, an LM26 temperature sensing IC, which will disable operation if the PCB temperature exceeds 85 C, and will re-enable once the temperature drops to 85 C. Converter Output Voltage (1 V/DIV) Secondary Reference Voltage VREF (0.5 V/DIV) SiP11203 reference voltage (TP18). The locations for these test points are shown in Figure 14. The bottom side component locations are also shown. Secondary MOSFET Gate Signal (5 V/DIV) 100 S/DIV Figure 13. Vo, Vref and OUTA on startup into an over-voltage. Test Points Several test points are provided on the topside of the demonstration board for ease of probing. These are the primary side MOSFET gate signals (TP10 and TP11), the primary current sense signal (TP16), primary VCC (TP14), pulse transformer primary signals SRL and SRH (TP3 and TP4), secondary side synchronous MOSFET gate signals (TP19 and TP20) and Document Number: 74254 S-60997-Rev. A, 12-Jun-06 Figure 14. SiP11203 Demonstration Board Component Layout www.vishay.com 7 SIP11203DB Vishay Siliconix PCB Layout and Bill of Materials The other PCB layers are shown in Figure 15 and Figure 16. The component listing is given in Table 4. Layer 1 Layer 2 Layer 3 Layer 4 Figure 15. SiP11203 Demonstration Board PCB layers 1-4 Layer 1 Layer 2 Layer 3 Layer 4 Figure 16. SiP11203 Demonstration Board PCB Layers 5-8 www.vishay.com 8 Document Number: 74254 S-60997-Rev. A, 12-Jun-06 SIP11203DB Vishay Siliconix PARTS LIST Line Number Reference Designator 1 C01 2 C02 3 C03 4 C04 5 C05 6 C06 7 C07 8 C08 9 C09 10 C10 11 C11 12 C12 13 C13 14 C14 15 C15 16 C16 17 C17 18 C18 19 C19 20 C20 21 C21 22 C22 23 C23 24 C24 25 C25 26 C26 27 C27 28 C28 29 C29 30 C31 31 C32 32 C33 33 C34 34 C36 35 D01 36 D03 37 D04 38 D06 39 D08 40 D09 41 D12 42 F01 43 44 45 46 47 48 49 50 J01 J03 J04 J05 J06 J07 J08 J09 Value/Type 6.8 nF, 50 V, X7R, 0603 470 pF, 50 V, X7R, 0603 220 nF, 10 V, X5R, 0603 NC 470 nF, 50 V, Y5V, 0603 10 pF, 50 V, X7R, 0603 47 pF, 50 V, NP0, 0603 1 uF, 50 V, X5R, 0603 1 nF, 50 V, X7R, 0603 1 uF, 50 V, X7R, 1210 1 uF, 50 V, X7R, 1210 1 uF, 50 V, X7R, 1210 1 uF, 50 V, X7R, 1210 1 uF, 50 V, X7R, 1210 1 uF, 50 V, X7R, 1210 1 uF, 50 V, X7R, 1210 1 uF, 50 V, X7R, 1210 220 pF, 50 V, NP0, 0603 100 nF, 50 V, Y5V, 0603 10 nF, 50 V, X7R, 0603 1 uF, 10 V, X5R, 0603 4.7 nF, 50 V, X7R, 0603 22 uF, 16 V, Tantalum, Case B 100 nF, 50 V, Y5V, 0603 6.8 nF, 50 V, X7R, 0603 100 nF, 50 V, Y5V, 0603 3.3 nF, 50 V, X7R, 0603 22 uF, 16 V, Tantalum, Case B 470 pF, 50 V, X7R, 0603 100 uF, 6.3 V, X5R, 1210 2.2 nF, 50 V, X7R, 0603 2.2 nF, 50 V, X7R, 0603 1 nF, 2 kV, X7R, 1206 220 pF, 50 V, NP0, 0603 25 V 200 mA Dual Schottky Diode SOT-23 1 A, 100 V Ultrafast Rectifier 0.2 A 200 V Switching Diode SOT23 4.3 V 300 mW Zener Diode SOD-323 400 mA, 40 V Schottky SOD-323 400 mA, 40 V Schottky SOD-323 6V8 300 mW Zener Diode SOD-323 3A Quick Blow 1206, 3216CP-3A PC PIN .040 DIA 3301 SERIES, 3301-2-14-21-00-00-08-0 PC PIN .040 DIA 3301 SERIES, 3301-2-14-21-00-00-08-0 PC PIN .040 DIA 3301 SERIES, 3301-2-14-21-00-00-08-0 PC PIN .040 DIA 3301 SERIES, 3301-2-14-21-00-00-08-0 PC PIN .040 DIA 3301 SERIES, 3301-2-14-21-00-00-08-0 PC PIN .040 DIA 3301 SERIES, 3301-2-14-21-00-00-08-0 PC PIN .040 DIA 3301 SERIES, 3301-2-14-21-00-00-08-0 PC PIN .040 DIA 3301 SERIES, 3301-2-14-21-00-00-08-0 Manufacturer Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay/Farnell/Digikey Part No. VJ0603Y682KXACW1BC VJ0603A471JXACW1BC VJ0603V224ZXJCW1BC VJ0603V474MXJCW1BC VJ0603A100JXACW1BC VJ0603A470JXACW1BC VJ0603G105KXQCW1BC VJ0603Y102KXACW1BC 490-1863-2-ND 490-1863-2-ND 490-1863-2-ND 490-1863-2-ND 490-1863-2-ND 490-1863-2-ND 490-1863-2-ND 490-1863-2-ND VJ0603A221JXACW1BC VJ0603V104MXACW1BC VJ0603Y103KXACW1BC VJ0603G105KXQCW1BC VJ0603Y472KXACW1BC 293D226X9016B2TE3 VJ0603V104MXACW1BC VJ0603Y682KXACW1BC VJ0603V104MXACW1BC VJ0603Y332KXACW1BC 293D226X9016B2TE3 VJ0603A471JXACW1BC 587-1388-1-ND VJ0603Y222KXACW1BC VJ0603Y222KXACW1BC 7569289 VJ0603A221JXACW1BC BAS40-06-GS08 ES1B-E3 BAS20-V-GS08 BZX384C4V3-V-GS08 ZHCS400CT-ND ZHCS400CT-ND BZX384C6V8-V-GS08 968912 ED5058-ND ED5058-ND ED5058-ND ED5058-ND ED5058-ND ED5058-ND ED5058-ND ED5058-ND www.vishay.com 9 Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Document Number: 74254 S-60997-Rev. A, 12-Jun-06 SIP11203DB Vishay Siliconix PARTS LIST Line Number Reference Designator 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 J10 L01 Q01 Q02 Q03 Q04 Q05 Q06 Q07 Q08 R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R30 R31 R32 R33 R35 R36 R37 T01 T02 U01 U02 U03 U04 PCB Value/Type PC PIN .040 DIA 3301 SERIES, 3301-2-14-21-00-00-08-0 E14/3.5/5, 3F3, 900nH, AL = 100 nH/T^2 100 V PowerPak 1212 MOSFET 100 V PowerPak 1212 MOSFET 20 V, PowerPak 1212 MOSFET 20 V, PowerPak 1212 MOSFET 20 V, PowerPak 1212 MOSFET 20 V, PowerPak 1212 MOSFET 50 V, 100 mA digital NPN transistor, SOT23 100 V, 5 A SOT223 PNP transistor 1k 0603 1 % 604R 0603 1 % 12k 0603 1 % 6k8 0603 1 % 5k1 0603 1 % 5k1 0603 1 % 560R 0603 1 % 560R 0603 1 % 5k1 0603 1 % NC 10k 0603 1 % 100k 0603 1 % 15k 0603 1 % 91k 0603 1 % 10k 0603 1 % NC 100R0 0603 1 % NC 100R0 0603 1 % 100k 0603 1 % 100k 0603 1 % 0R015 2010 1 % 100R0 0603 1 % 100R0 0603 1 % 4k7 0603 1 % 56k 0603 1 % 30k 0603 1 % 56k 0603 1 % 1MEG 0603 1 % 4R7 0603 1 % 4R7 0603 1 % 0R0 0603 1 % 47R 1206 1 % 47R 1206 1 % 12k 0603 1 % E8.8-T38 E14/3.5/5, 3F3, 4:1:1 Si9122 Half Bridge Controller 'Mulligan' Secondary Side Controller TMCT1102 Opto-coupler Digital thermostat with preset trip, LM26CIM5-TPA, SOT23 SiP9122/SiP11203 demo board PCB Table 4. Manufacturer Vishay/Farnell/Digikey Part No. ED5058-ND Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Si7810DN-T1-E3 Si7810DN-T1-E3 Si7108DN-T1-E3 Si7108DN-T1-E3 Si7108DN-T1-E3 Si7108DN-T1-E3 MMUN2213LT1OSCT-ND ZX5T953GCT-ND CRCW06031K00FKEA CRCW0603604RFKEA CRCW060312K0FKEA CRCW06036K80FKEA CRCW06035K10FKEA CRCW06035K10FKEA CRCW0603560RFKEA CRCW0603560RFKEA CRCW06035K10FKEA CRCW060310K0FKEA CRCW0603100KFKEA CRCW060315K0FKEA CRCW060391K0FKEA CRCW060310K0FKEA CRCW0603100RFKEA CRCW0603100RFKEA CRCW0603100KFKEA CRCW0603100KFKEA WSL2010R0150FEA CRCW0603100RFKEA CRCW0603100RFKEA CRCW06034K70FKEA CRCW060356K0FKEA CRCW060330K0FKEA CRCW060356K0FKEA CRCW06031M00FKEA CRCW06034R70FKEA CRCW06034R70FKEA CRCW06030000Z0EA CRCW120647R0FKEA CRCW120647R0FKEA CRCW060312K0FKEA 926462 / 926474 Si9122 SiP11203 TCMT1102 4125125 Vishay Vishay Vishay www.vishay.com 10 Document Number: 74254 S-60997-Rev. A, 12-Jun-06 SIP11203DB Vishay Siliconix Host Board Fixture Schematic, Layout and Bill of Materials The schematic and PCB layers are shown in Figure 17 and Figure 18. The component listing is given in Table 5. DCDC_ENA J6-1 VIN TP1 VIN J4-1 + J1-2 TP2 VIN RTN PRI_GND J9-1 VOUT J3-3 C1 + C2 J5-1 J8-1 TP5 VOUT J3-2 J7-1 TP4 VOUT_SENSE J3-1 J1-1 R1 J2-1 TP3 DCDC_ENA OPTIONAL OR J10-1 TP6 VOUT RTN J3-4 J2-2 PRI_GND J11-1 VOUT RTN J3-5 SEC_GND VOUT_SENSE RTN J3-6 VIN J12-1 TP7 R2 S1 R3 R1 DCDC_ENA PRI_GND OPTIONAL OR PRI_GND Figure 17. Host Board Fixture Schematic Figure 18. Host Board Fixture PCB Layers Document Number: 74254 S-60997-Rev. A, 12-Jun-06 www.vishay.com 11 SIP11203DB Vishay Siliconix PARTS LIST Per Board 2 2 1 1 1 2 1 9 4 3 1 Reference Designator C1, C2 R1, R4 R2 R3 S1 J1, J2 J3 J4-J12 TP1, TP3, TP4, TP5 TP2, TP6, TP7 PCB Value/Type 47 uF, 160 V EEUED2C470 0R0 link 1206 16k, 1206 1k1 1206 Switch PCB, SPDT Terminal Block, 3.81 mm, 2 way, 10 A Terminal Block, 3.81 mm, 6 way, 10 A Socket 1.0 mm PCB hole 1.93 mm H3161-01 Red PCB Terminal Black PCB Terminal SiP9122/SiP11203 demo board test fixture PCB Table 5. Manufacturer Vishay Vishay Vishay Vishay Vishay/Farnell/Digikey Part No. EKV00FE247M00K CRCW12060000Z0EA CRCW120616K0FKEA CRCW12061K10FKEA 9574590 3704579 3704610 149318 8731144 8731128 NOTICE Preliminary datasheet of the products contains preliminary information are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale. www.vishay.com 12 Document Number: 74254 S-60997-Rev. A, 12-Jun-06 |
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